The present invention relates to a technique effective for use in a digital signal transmission or a signal transmission taking on more than three levels of a transmission line, for example, to a technique effective for use in a simultaneous bi-directional data transmission system or a signal transmission system by multi-value levels.
Conventionally, a simultaneous bi-directional interface called SBTL is known which permits simultaneous data transmissions from both ends of the transmission line. In the simultaneous bi-directional interface, a bi-directional data transmission is carried out on one transmission line, and the level on the transmission line assumes any one of three levels, namely, low level, high level, and the medium level of the two, in accordance with the combination of the two data transmitted from the both ends. Therefore, a system is adopted which provides two reference voltages (logic determination levels) to the input buffer (comparator) on the reception end to thereby discriminate reception data.
The conventional simultaneous bi-directional interface includes an output buffer OBF and an input buffer IBF and a reference voltage generation circuit VRG in each chip, as shown in FIG. 11, and varies the reference voltages generated by the reference voltage generation circuit VRG in accordance with the self transmission data TDATA-A, TDATA-B as illustrated by the dotted lines in FIG. 12(a) and FIG. 12(b), and thereby discriminates the reception data RDATA-B, RDATA-A, which is a generally applied system.
However, the switching system of the reference voltages involves a problem that the switching of the reference voltages increases the jitter (shift in varying timing) of the reception data. This is because the switching of the reference voltages with one input buffer creates a deviation in the timing of determination (point of the reception data waveform crossing the reference voltages), when the reference voltages are high and low even with the same reception data. In case the reference level varies when the reception data vary, the timing of determination deviates in the case that the varying direction of the reference level is coincident with the varying direction of the reception data, and also in the case opposite to the former case.
On the other hand, as a simultaneous bi-directional interface proposed conventionally, a technique is disclosed in the Japanese Published Unexamined Patent Application No. Hei 8 (1996)-107346, which provides two input buffers (comparators) having different reference levels, brings both the two input buffers into operation, switches the selectors in the post-stage in accordance with the self transmission data, and thereby takes in data determined by the reference level according to the transmission data.